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|ID||Project||Category||View Status||Date Submitted||Last Update|
|0000243||Firmware||Init & Config||public||2011-07-28 23:00||2014-02-18 23:46|
|Target Version||0.2.0||Fixed in Version||0.2.0|
|Summary||0000243: Handle Spurious Interrupts & Other System Interrupts|
|Description||Currently there is no handler (UISR) for the spurious interrupt vector and several others which are out of our control. This is bad. Add handlers for all non-peripheral system level interrupts such that program operation is ensured to be smooth at all times.|
|Tags||No tags attached.|
|Risk of Breakage||very low|
|Currently broken, can only get better from here.|
COP and Main reset vectors - These are handled by the SM.
CRG self clock
CRG PLL lock
COP, main, and clock are all passed through the SM vector table, and can't be handled by us directly. Later it'd be nice to see from where each reset came, this requires SM mods.
The two CRG interrupts are now active and in use, issues are 0000213 and 0000844 detail this.
That leaves Spurious, Unimplemented, RAM Violation and XGATE software error to do. Perhaps others? I don't think so, but maybe.
|Sean, this is fixed in hash 22572c7, please rebase your XGATE stuff on top of this, add some bad instructions and verify that the four bits in the new flags register remain unset without the bad instructions and the xg sw error becomes set with it. Close if happy.|
|Closing as no one has complained about anything, so it's likely fine. Typical lack of testing and community involvement demonstrated here by Sean... utter FAIL!|
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